What do the makefile symbols $@ and $< mean?
CC=g++
CFLAGS=-c -Wall
LDFLAGS=
SOURCES=main.cpp hello.cpp factorial.cpp
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=hello
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(LDFLAGS) $(OBJECTS) -o $@
.cpp.o:
$(CC) $(CFLAGS) $< -o $@
$@和$<做什么？
$@ is the name of the file being generated, and $< the first prerequisite (usually the source file). You can find a list of all these special variables in the GNU Make manual.
For example, consider the following declaration:
all: library.cpp main.cpp
In this case:
$@ evaluates to all $< evaluates to library.cpp $^ evaluates to library.cpp main.cpp The $@ and $< are called the automatic variables. The $@ is the output variable. $< is the first input variable. For example:
hello.o: hello.c hello.h
gcc -c $< -o $@
Here, hello.o is the output file. This is what $@ expands to. The first dependency is hello.c . That's what $< expands to.
The -c flag generates the .o file; see man gcc for a more detailed explanation. The -o specifies the file to output to.
For further details, you can read this.
Also, you can check the GNU manuals. There is a way to debug your makefile to understand it better.
This will output the makefile database:
$make -p
The $@ and $< are special macros.
Where:
$@ is the file name of the target.
$< is the name of the first dependency.